With the high integration of the semiconductor devices, characteristics of the semiconductor devices can be degraded, in particular, operation current of a transistor in a peripheral circuit area may be reduced and a speed of the semiconductor device may be reduced. That is, the factor related to current flow at any given time may be degraded and this total speed of the semiconductor reduced.
To improve the speed of the semiconductor device, new technology such as a junctionless transistor has suggested, but it may be difficult to apply the new technology to the current structure of the semiconductor device and to integrate the junctionless transistor currently.
As the semiconductor device is highly integrated, a gate insulating layer having a thin thickness can suppress a short channel effect and adjust a threshold voltage in the transistor. However, as the thickness of the gate insulating layer is thinned, leakage current of the transistor may be increased by tunneling of a gate electrode, or a failure such as dielectric breakdown in the gate insulating layer can occur.
A high dielectric (high-k) material may be applied as the gate insulating layer to address the above-described issue. With application of the high-k gate insulating layer, it is possible to suppress the short channel effect and to adjust the threshold voltage in the transistor with stable characteristics for the leakage current and dielectric breakdown generated in the gate insulating layer. Thus miniaturization, high integration, and high speed operation of the semiconductor device are possible.
However, the application of the high-k gate insulating layer may not improve leakage current of the transistor by gate-induced drain leakage (GIDL) due to concentration of the electric field generated in an overlapping region of the drain and gate, and the high integration of the semiconductor device may be difficult.